1. Field of the Invention
The present invention relates to an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same.
2. Description of the Related Art
A phase locked loop (PLL) circuit is widely used to generate an application carrier frequency in a 4th-generation mobile communications system such as long term evolution (LTE), or the like, a cellular phone technology such as Bluetooth™, a global positioning system (GPS), a wideband code division multiple access (WCDMA) scheme, or the like, a wireless local area network (WLAN) such as an 802.11a/b/g scheme, or the like. A related art analog PLL circuit has a problem in that it requires a divider operable at high speed, and since a width-length ratio of a metal-oxide semiconductor (MOS) may be limited depending on noise, accuracy, or the like, of a current source, the area thereof cannot be reduced.
Also, since a loop filter includes a passive resistor and a capacitor, it takes up a relatively large area, and in order to secure a desired analog signal level, a voltage-controller oscillator (VCO) buffer, a local oscillator (LO) buffer, an output buffer, or the like, is required in order to increase power consumption. In addition, when a process is changed, all the blocks are required to be substantially re-designed due to the sensitivity to process characteristics of the analog PLL circuit, increasing a fabrication time and manufacturing costs. Thus, demand for a digital PLL circuit in which the foregoing problems are able to solved has been ongoing.
A digital PLL circuit is a block for converting an analog signal into a digital signal, which may include a time-to-digital converter (TDC). The TDC includes one or more delay cells, and a delay time of each delay cell may be increased or decreased according to a process, a supply voltage, a temperature, and the like, such as PVT (Process, Voltage, and Temperature) conditions. Thus, a technique for effectively compensating for a change in a delay time according to the PVT conditions, or the like, is required in the design stage of a TDC.
Patent Document 1 relates to a TDC and proposes a TDC as an analog-to-digital converter applicable to a digital PLL circuit, but without the disclosure of content regarding an auxiliary delay cell and content of compensating for a change in a delay time of each delay cell. Also, Patent Document 2 discloses content of outputting two digital signals from different TDCs, but without content of compensating for a change in a delay time by using the two digital signals.